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PRELIMINARY
CY2281
100MHz Pentium(R)II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs
Features
* Mixed 2.5V and 3.3V operation * Complete clock solution for Pentium(R) II, and other similar processor-based motherboards -- Two CPU clocks at 2.5V up to 100 MHz -- Six synchronous PCI clocks, one free-running -- One 3.3V Ref. clock at 14.318 MHz * * * * * -- One 3.3V USB clock at 48 MHz (-2S only) Spread Spectrum clocking for EMI control (-11S, -2S) 1.5-4.0 ns delay between CPU and PCI clocks Power-down, CPU stop and PCI stop pins Low skew outputs, 175 ps between CPU clocks Factory-EPROM programmable output drive and slew rate for EMI customization * Available in space-saving 28-pin SSOP package duce EMI in certain high-speed systems. A summary of clock outputs for both devices is shown below. The part possesses power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2281 clock outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2281 to have lower EMI than clock devices from other manufacturers. Additionally, factory-EPROM programmable output drive and slew-rate control enable optimal configurations.
Functional Description
The CY2281 is a clock synthesizer/driver for Pentium II, or other similar processor-based mobile PCs requiring up to 100 MHz support. The CY2281 outputs two CPU clocks at 2.5V. There are six PCI clocks, running at one-half or one-third the CPU clock frequency of 66.6 MHz and 100 MHz respectively. One of the PCI clocks is free-running. Additionally, the part outputs one 3.3V reference clock at 14.318 MHz. The CY2281-2S also provides one 3.3V USB clock at 48 MHz. The CY2281-11S and CY2281-2S incorporate the Intel(R)-defined spread spectrum feature. They provide a -0.6% downspread on the CPU and PCI clocks, which can help re-
CY2281 Selector Guide
Clock Outputs CPU (66, 100 MHz) PCI (CPU/2, CPU/3) REF (14.318 MHz) USB (48 MHz) CPU-PCI delay Spread Spectrum
Note: 1. One free-running PCI clock.
-1 2 6[1] 1 N/A 1.5-4.0 ns None
-11S 2 6[1] 1 N/A 1.5-4.0 ns -0.6%
-2S 2 6[1] 1 1 1.5-4.0 ns -0.6%
Logic Block Diagram
Pin Configuration
28-Pin SSOP Top View
CPU_STOP XTALIN
XTALOUT
REF
14.318 MHz OSC. CPU PLL Divider STOP LOGIC
XTALIN XTALOUT VSS PCICLK_F PCICLK1 VDDPCI PCICLK2 PCICLK3 VDDPCI PCICLK4 PCICLK5 VSS VDDUSB VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY2281
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS VDDREF REF VDDCPU CPUCLK0 CPUCLK1 VSS AVDD VSS PCI_STOP CPU_STOP PWR_DWN SEE CHART BELOW SEL100
VDDREF CPUCLK [0-1] VDDCPU PCICLK_F
EPROM Delay STOP LOGIC
PWR_DWN SEL (-1/-11S only) SEL100
VDDPCI PCI [1-5] VDDPCI
SYS PLL
USBCLK (-2S only)
Option Pin 16 SEL USBCLK
VDDUSB PCI_STOP
-1,-11S -2S
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 July 21, 1999
PRELIMINARY
Pin Summary
Name VDDPCI VDDREF VDDCPU VDDUSB AVDD VSS XTALIN
[2]
CY2281
Pins 6, 9 27 25 13 21 3, 12, 14, 20, 22, 28 1 2 19 18 17 16 16 15 23, 24 5, 7, 8, 10, 11 4 26
Description 3.3V Digital voltage supply for PCI clocks 3.3V Digital voltage supply for REF clocks 2.5V Digital voltage supply for CPU clocks 3.3V Digital voltage supply for USB clock Analog voltage supply, 3.3V Ground Reference crystal input Reference crystal feedback Active LOW control input to stop PCI clocks Active LOW control input to stop CPU clocks Active LOW control input to power down device CPU frequency select input (-1 and -11S options only) USB clock output, 48 MHz fixed (-2S option only) CPU frequency select input, selects between 100 MHz and 66.6 MHz (see table below) CPU clock outputs PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz or 100 MHz respectively Free-running PCI clock output 3.3V Reference clock output
XTALOUT[2] PCI_STOP CPU_STOP PWR_DWN SEL USBCLK SEL100 CPUCLK[0:1] PCICLK[1:5] PCICLK_F REF
Function Table
SEL100 0 0 1 1 SEL[4] 0 1 0 1 CPU/PCI Ratio 2 2 3 3 CPUCLK Hi-Z 66.66 MHz TCLK/2 100 MHz PCICLK_F PCICLK Hi-Z 33.33 MHz TCLK/6 33.33 MHz 48 MHz 48 MHz USBCLK[5] REF Hi-Z 14.318 MHz TCLK[3] 14.318 MHz
Notes: 2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. 3. TCLK supplied on the XTALIN pin in Test Mode. 4. SEL available on options -1 and -11S only. SEL tied HIGH internally on option -2S 5. USBCLK available on option -2S only.
2
PRELIMINARY
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK USB Target Frequency Actual Frequency (MHz) (MHz) 66.67 100 48 66.654 99.77 48.008 PPM -195 -2346 167
CY2281
Power Management Logic
CPU_STOP X 0 0 1 1 PCI_STOP X 0 1 0 1 PWR_DWN 0 1 1 1 1 CPUCLK Low Low Low Running Running PCICLK Low Low Running Low Running PCICLK_F Low Running Running Running Running Other Clocks Low Running Running Running Running Osc. Off PLLs Off
Running Running Running Running Running Running Running Running
3
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ............................................... -0.5V to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5
CY2281
Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Static Discharge Voltage .......................................... >1700V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[6]
Parameter Description Min. 3.135 2.375 0 Max. 3.465 2.625 70 20 30 20 14.318 14.318 MHz Unit V V C pF AVDD, VDDPCI, Analog and Digital Supply Voltage VDDREF, VDDUSB VDDCPU TA CL CPU Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK PCICLK REF Reference Frequency, Oscillator Nominal Value
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VOH VOL VOH VOL IIH IIL IOZ IDD25 IDD25 IDD33 IDDS Description High-level Input Voltage Low-level Input Voltage Low-level Output Voltage Except Crystal Inputs
[7]
Test Conditions Except Crystal Inputs[7] IOH = 12 mA IOL = 12 mA IOH = 16 mA CPUCLK CPUCLK
Min. Max. Unit 2.0 0.8 2.0 0.4 2.4 0.4V -10 -10 +10 10 +10 70 100 170 500 V V V V V V A A A mA mA mA A
High-level Output Voltage VDDCPU = 2.375V VDDCPU = 2.375V High-level Output Voltage VDDPCI, AVDD, VDDREF = 3.135V Low-level Output Voltage Input High Current Input Low Current Output Leakage Current Power Supply Current for 2.5V Clocks Power Supply Current for 2.5V Clocks Power Supply Current for 3.3V Clocks Powerdown Current VDDPCI, AVDD, VDDREF = 3.135V VIH = V DD VIL = 0V Three-state
IOH = 14.5 mA PCICLK REF, USB PCICLK REF, USB IOL = 9.4 mA IOL = 9 mA
VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.6 MHz VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs Current draw in powerdown state
Notes: 6. Electrical parameters are guaranteed with these operating conditions. 7. Crystal Inputs have CMOS thresholds.
4
PRELIMINARY
Switching Characteristics[8] Over the Operating Range
Parameter t1 t2 t2 t2 t3 t4 t5 t6 t7 t10 t11 t12 Output All CPUCLK PCICLK REF, USB CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK PCICLK, PCICLK CPUCLK PCICLK CPUCLK, PCICLK Description Output Duty Cycle
[9]
CY2281
Test Conditions t1 = t1A / t1B Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V Between 2.0V and 0.4V Measured at 1.25V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.25V Measured at 1.5V CPU and PCI clock stabilization from power-up
Min. 45 0.85 1.0 0.5 0.4 0.4
Typ. 50
Max. 55 4.0 4.0 2.0 1.6 1.6
Unit % V/ns V/ns V/ns ns ns ps ns ps ps ps ms
CPU Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate REF Clock Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew PCI-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
100 1.5
175 4.0 250 550 550 3
Notes: 8. All parameters specified with loaded outputs. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
Switching Waveforms
Duty Cycle Timing
t1A OUTPUT t1B
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3 t2 t4
CPU-CPU Clock Skew
CPUCLK
CPUCLK t5
5
PRELIMINARY
Switching Waveforms (continued)
CPU-PCI Clock Skew
CPUCLK
CY2281
PCICLK t6
PCI-PCI Clock Skew
PCICLK
PCICLK t7
CPU_STOP
CPUCLK (Internal) PCICLK (Internal) PCICLK
(Free-Running)
CPU_STOP CPUCLK (External)
PCI_STOP
CPUCLK (Internal) PCICLK (Internal) PCICLK
(Free-Running)
PCI_STOP PCICLK (External)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
6
PRELIMINARY
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
CY2281
Application Circuit
XTALIN XTALOUT Cx
PWR_DWN# CPU_STOP# PCI_STOP# SEL SEL100 VDD 3.3V Cd 0.1F VDD 2.5V Cd 0.1F
PWR_DWN# CPU_STOP# REF PCI_STOP# CPUCLK PCICLK SEL PCICLK_F SEL100
Rs REF CPUCLK PCICLK PCICLK_F
VDDPCI/VDDREF AVDD/VDDUSB
VDDCPU
Ct
VSS CY2281 28-PIN SSOP Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI-REDUCING CAPACITORS Cx = OPTIONAL LOAD MATCHING CAPACITOR Rs = SERIES TERMINATING RESISTORS
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F-22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
7
PRELIMINARY
CY2281
Test Circuit
VDDPCI, AVDD, VDDREF 0.1 F
3, 12, 14, 20, 22, 28 6, 9, 13, 21, 27 CY2281-1,-11S, -2S
VDDCPU OUTPUTS 25 0.1 F Notes: Each supply pin must have an individual decoupling capacitor All capacitors must be placed as close to the pins as is possible. CLOAD
Ordering Information
Ordering Code CY2281PVC-1 CY2281PVC-11S CY2281PVC-2S Document #: 38-00660-C Package Name O28 O28 O28 Package Type 28-Pin SSOP 28-Pin SSOP 28-Pin SSOP Operating Range Commercial Commercial Commercial
8
PRELIMINARY
Package Diagram
28-Lead (210-Mil) Shrunk Small Outline Package O28
CY2281
51-85079-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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